1. Field of the Invention
The present invention relates to a constant voltage circuit, and more particularly to a constant voltage circuit which is capable of quickly responding to a sudden change of a load current.
2. Discussion of the Background
A background constant voltage circuit has a function to rapidly compensate for decreases in an output voltage due to a sudden rise of a load current. In this compensation, the circuit simply detects an alternating current element in the varying output voltage and supplies a compensation current to the load from a power source voltage based on the detection result, thereby compensating a sudden decrease of the output voltage. For this operation, the circuit is provided with a coupling capacitor for the detection and an additional transistor for the compensation current different from an output transistor.
FIG. 1 illustrates a constant voltage circuit 100 as an example of such background constant voltage circuit. The constant voltage circuit 100 of FIG. 1 has an improved responsiveness to a sudden rise of a load current consumed by a load 10. The improvement is achieved by a control of a output transistor M1 to change an output voltage using a second error amplifier AMPb having a fast response speed. This example does not require an additional transistor for the compensation current different from an output transistor.
More details of the constant voltage circuit 100 of FIG. 1 is explained below. As illustrated in FIG. 1, the constant voltage circuit 100 includes a first reference voltage generator (1st RVG) 2, a second reference voltage generator (2nd RVG) 3, and a third reference voltage generator (3rd RVG) 4. The first reference voltage generator 2 generates and outputs a predetermined reference voltage Vr. The second reference voltage generator 3 generates and outputs a predetermined reference voltage Vb1. The third reference voltage generator 4 generates and outputs a predetermined bias voltage Vb2. The constant voltage circuit 100 further includes resistors R1 and R2, a output transistor M1, and an error amplifying circuit 105. The resistors R1 and R2 divide an output voltage Vout to generate a divided voltage VFB. The output transistor M1 includes a P-MOS (P-type metal oxide semiconductor) transistor which, based on an input signal to a gate thereof, controls a current io flowing through an output terminal OUT. The error amplifying circuit 105 controls an operation of the output transistor M1 such that the divided voltage VFB is equalized to the reference voltage Vr.
The error amplifying circuit 105 includes first and second error amplifiers AMPa and AMPb. The first error amplifier AMPa has a non-inverse input terminal to which the reference voltage Vr is input and an inverse input terminal to which the divided voltage VFB is input. The second error amplifier AMPb has a non-inverse input terminal to which the reference voltage Vb1 is input and an inverse input terminal to which the output voltage Vout is input. Each of the first and second error amplifiers AMPa and AMPb outputs a signal for controlling the operation of the output transistor M1 so as to control the output voltage Vout.
The first error amplifier AMPa is configured to have a gain of a direct current as great as possible so as to produce a superior direct current characteristic. More, specifically, in the first error amplifier AMPa, a N-MOS (N-type metal oxide semiconductor) transistor M2 serving as a constant current source generates a drain current as small as possible. On the other hand, the second error amplifier AMPb is configured to amplify only an alternating current element of the output voltage Vout. To make it, in the second error amplifier AMPb, a P-MOS transistor M11 has a gate connected to the output terminal OUT via a capacitor C3 operating as a coupling capacitor.
The first error amplifier AMPa has any particular difference from the one used in a common constant-voltage circuit. Therefore, no further details on the first error amplifier AMPa are explained.
The second error amplifier AMPb has a two-stage amplifying structure, and includes a differential amplifying circuit as a first stage and a N-MOS transistor M14 as a second stage. The differential amplifying circuit includes P-MOS transistors M9, M10, and M11, and N-MOS transistors M12 and M13. The P-MOS transistors M10 and M11 form a differential pair, and one of them is configured to have an offset voltage so that the P-MOS transistor M11 is in an off state when the output voltage Vout is in a stable state. The drain voltage of the P-MOS transistor M11 is therefore 0 volts. As a consequence, the N-MOS transistor M14 is turned off and does not affect the control of the output transistor M1.
When the output voltage Vout is suddenly decreased due to a steep change of the load, for example, it causes the gate voltage of the P-MOS transistor M11 to be decreased via the coupling capacitor C3. The gate voltage of the P-MOS transistor M10 is also decreased but with a slight delay from the decrease of the gate voltage of the P-MOS transistor M11 by an action of the resistor R4. As a result, the P-MOS transistor M11 is turned on and the drain voltage thereof is increased again. Upon a time the drain voltage of the P-MOS transistor M11 exceeds a threshold value of the gate voltage of the N-MOS transistor M14, the N-MOS transistor M14 is turned on and accordingly causes the output transistor M1 to reduce the gate voltage thereof. Consequently, the output transistor M1 is caused to increase the drain current by which the output voltage Vout is increased to the predetermined voltage.
In this configuration, the response speed of the second error amplifier AMPb is faster than that of the first error amplifier AMPa. Therefore, it becomes possible to return the output voltage Vout to the predetermined voltage before the first error amplifier AMPa is activated to compensate a reduction of the output voltage Vout.
On the other hand, when the output voltage Vout is increased, the P-MOS transistor M11 is affected via the coupling capacitor C3 in a way to increase the gate voltage thereof. However, at this time, the P-MOS transistor M11 is held in an off-state and therefore the N-MOS transistor M14 also maintains in an off-state. Accordingly, the control of the output transistor M1 is not affected.
In the constant voltage circuit 100 of FIG. 1, the coupling capacitor C3 may be configured to have a greater capacitance to increase a sensitivity to a change of the output voltage Vout. In this case, however, the gate voltage of the output transistor M1 is excessively lowered particularly at a power-on time, or when the output voltage Vout is largely decreased due to a significant change of the load current. FIG. 2 illustrates a typical overshoot of the output voltage Vout at a recovery to the predetermined voltage after such an excessive reduction of the gate voltage of the output transistor M1. As illustrated in FIG. 1, this overshoot may cause an oscillation when the overshoot voltage is returned to the predetermined voltage. That is, the second error amplifier AMPb is again activated to increase the output voltage Vout.
On the other hand, if the coupling capacitor C3 is configured to have a relatively small capacitance, the above-described overshoot may be avoided. However, the sensitivity to the change of the output voltage Vout is lowered and, as a result, a relatively small change of the output voltage Vout cannot be compensated.